Publication:

Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM

Date

2021
Proceedings Paper
https://doi.org/10.23919/DATE51398.2021.9473999
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dc.contributor.authorWu, Lizhou
dc.contributor.authorRao, Siddharth
dc.contributor.authorTaouil, Mottaqiallah
dc.contributor.authorMarinissen, Erik Jan
dc.contributor.authorKar, Gouri Sankar
dc.contributor.authorHamdioui, Said
dc.contributor.imecauthorRao, Siddharth
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.orcidimecRao, Siddharth::0000-0001-6161-3052
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.date.accessioned2022-08-18T14:05:30Z
dc.date.available2022-07-18T02:27:52Z
dc.date.available2022-07-19T09:19:41Z
dc.date.available2022-08-18T14:05:30Z
dc.date.embargo9999-12-31
dc.date.issued2021
dc.identifier.doi10.23919/DATE51398.2021.9473999
dc.identifier.eisbn978-3-9819263-5-4
dc.identifier.issn1558-1101
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/40136
dc.publisherIEEE
dc.source.beginpage1717
dc.source.conferenceDesign, Automation and Test in Europe Conference and Exhibition (DATE)
dc.source.conferencedateFEB 01-05, 2021
dc.source.conferencelocationGrenoble
dc.source.endpage1722
dc.source.journalna
dc.source.numberofpages6
dc.subject.disciplineElectrical & electronic engineering
dc.subject.keywordsSTT-MRAM, MRAM, testing, embedded memory
dc.title

Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM

dc.typeProceedings paper
dspace.entity.typePublication
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