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Circuit-level modeling of Finfet sub-threshold slope and DIBL mismatch beyond 22nm

Date

2013
Proceedings Paper
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dc.contributor.authorRoyer Del Barrio, Pablo
dc.contributor.authorZuber, Paul
dc.contributor.authorCheng, Binjie
dc.contributor.authorAsenov, Asen
dc.contributor.authorLopez-Vallejo, M.
dc.contributor.imecauthorZuber, Paul
dc.date.accessioned2021-10-21T11:35:18Z
dc.date.available2021-10-21T11:35:18Z
dc.date.embargo9999-12-31
dc.date.issued2013
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23020
dc.source.beginpage204
dc.source.conferenceInternational Conference on Simulation of Semiconductor Processes and Devices - SISPAD
dc.source.conferencedate3/09/2013
dc.source.conferencelocationGlasgow UK
dc.source.endpage207
dc.title

Circuit-level modeling of Finfet sub-threshold slope and DIBL mismatch beyond 22nm

dc.typeProceedings paper
dspace.entity.typePublication
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