Publication:

Manufacturable processes for =32-nm-node CMOS enhancement by synchronous optimization of strain-engineered channel and external parasitic resistances

Date

2008
Journal article
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dc.contributor.authorNoori, Atif
dc.contributor.authorBalseanu, Mihaela
dc.contributor.authorBoelen, Pieter
dc.contributor.authorCockburn, Andrew
dc.contributor.authorDemuynck, Steven
dc.contributor.authorFelch, Susan
dc.contributor.authorGandikota, Srinivas
dc.contributor.authorGelatos, jerry
dc.contributor.authorKhandelwal, Amit
dc.contributor.authorKittl, Jorge
dc.contributor.authorLauwers, Anne
dc.contributor.authorLee, Wen-Chin
dc.contributor.authorLei, Jianxin
dc.contributor.authorMandrekar, Tushar
dc.contributor.authorSchreutelkamp, Rob
dc.contributor.authorShah, Kavita
dc.contributor.authorThompson, Scott
dc.contributor.authorVerheyen, Peter
dc.contributor.authorWang, Ching-Ya
dc.contributor.authorXia, Li-Qun
dc.contributor.imecauthorCockburn, Andrew
dc.contributor.imecauthorDemuynck, Steven
dc.contributor.imecauthorLauwers, Anne
dc.contributor.imecauthorVerheyen, Peter
dc.date.accessioned2021-10-17T09:20:12Z
dc.date.available2021-10-17T09:20:12Z
dc.date.issued2008
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/14223
dc.source.beginpage1259
dc.source.endpage1264
dc.source.issue5
dc.source.journalIEEE Transactions on Electron Devices
dc.source.volume55
dc.title

Manufacturable processes for =32-nm-node CMOS enhancement by synchronous optimization of strain-engineered channel and external parasitic resistances

dc.typeJournal article
dspace.entity.typePublication
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