Publication:

12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices

Date

2019
Proceedings Paper
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dc.contributor.authorKim, Min-Soo
dc.contributor.authorHarada, N.
dc.contributor.authorKikuchi, Yoshiaki
dc.contributor.authorBoemmels, Juergen
dc.contributor.authorMitard, Jerome
dc.contributor.authorHuynh Bao, Trong
dc.contributor.authorMatagne, Philippe
dc.contributor.authorTao, Zheng
dc.contributor.authorLi, Waikin
dc.contributor.authorDevriendt, Katia
dc.contributor.authorRagnarsson, Lars-Ake
dc.contributor.authorLorant, Christophe
dc.contributor.authorSebaai, Farid
dc.contributor.authorPorret, Clément
dc.contributor.authorRosseel, Erik
dc.contributor.authorDangol, Anish
dc.contributor.authorBatuk, Dmitry
dc.contributor.authorMartinez Alanis, Gerardo Tadeo
dc.contributor.authorGeypen, Jef
dc.contributor.authorJourdan, Nicolas
dc.contributor.imecauthorKim, Min-Soo
dc.contributor.imecauthorKikuchi, Yoshiaki
dc.contributor.imecauthorBoemmels, Juergen
dc.contributor.imecauthorMitard, Jerome
dc.contributor.imecauthorMatagne, Philippe
dc.contributor.imecauthorTao, Zheng
dc.contributor.imecauthorLi, Waikin
dc.contributor.imecauthorDevriendt, Katia
dc.contributor.imecauthorRagnarsson, Lars-Ake
dc.contributor.imecauthorLorant, Christophe
dc.contributor.imecauthorSebaai, Farid
dc.contributor.imecauthorPorret, Clément
dc.contributor.imecauthorRosseel, Erik
dc.contributor.imecauthorDangol, Anish
dc.contributor.imecauthorBatuk, Dmitry
dc.contributor.imecauthorMartinez Alanis, Gerardo Tadeo
dc.contributor.imecauthorGeypen, Jef
dc.contributor.imecauthorJourdan, Nicolas
dc.contributor.imecauthorSepulveda Marquez, Alfonso
dc.contributor.imecauthorPuliyalil, Harinarayanan
dc.contributor.orcidimecKim, Min-Soo::0000-0003-0211-0847
dc.contributor.orcidimecMitard, Jerome::0000-0002-7422-079X
dc.contributor.orcidimecDevriendt, Katia::0000-0002-0662-7926
dc.contributor.orcidimecRagnarsson, Lars-Ake::0000-0003-1057-8140
dc.contributor.orcidimecLorant, Christophe::0000-0001-7363-9348
dc.contributor.orcidimecPorret, Clément::0000-0002-4561-348X
dc.contributor.orcidimecBatuk, Dmitry::0000-0002-6384-6690
dc.contributor.orcidimecMartinez Alanis, Gerardo Tadeo::0000-0001-5036-0491
dc.contributor.orcidimecSepulveda Marquez, Alfonso::0000-0003-4726-177X
dc.contributor.orcidimecPuliyalil, Harinarayanan::0000-0002-9749-5307
dc.contributor.orcidimecJamieson, Geraldine::0000-0002-6750-097X
dc.contributor.orcidimecvan der Veen, Marleen::0000-0002-9402-8922
dc.contributor.orcidimecTeugels, Lieve::0000-0002-6613-9414
dc.date.accessioned2021-10-27T11:29:59Z
dc.date.available2021-10-27T11:29:59Z
dc.date.embargo9999-12-31
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/33297
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8776532
dc.source.beginpageT15-1
dc.source.conference2019 Symposium on VLSI Technology
dc.source.conferencedate9/06/2019
dc.source.conferencelocationKyoto Japan
dc.title

12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices

dc.typeProceedings paper
dspace.entity.typePublication
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