2D Local Interconnect Metal Patterning Exploration for CFET

Abstract

To keep up with the pace set by Moore's law, an innovative standard cell architecture called CFET has been proposed recently. Its technical challenge is to stack transistors on top of each other to achieve higher density. Nevertheless, the targeted nodes still require very small dimensions in terms of pitches, critical dimensions (CD) and tip-to-tip, but also in terms of geometries. In this paper we explore the patterning of a 2D local interconnect, Middle of the Line (MOL) layer with aggressive pitches and spaces that has been foreseen as a possible option for this CFET architecture. Multiple patterning solutions are proposed including 1-EUV print with multiple colors, 2-Spacer assisted solutions with multiple cut patterns. Finally, we evaluate the benefit of using 3-High NA EUV lithography as a potential candidate for this type of layer.