Publication:

Benchmarking of MoS2 FETs with multigate Si-FET options for 5 nm and beyond

Date

2015
Journal article
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dc.contributor.authorAgarwal Kumar, Tarun
dc.contributor.authorYakimets, Dmitry
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorRadu, Iuliana
dc.contributor.authorThean, Aaron
dc.contributor.authorHeyns, Marc
dc.contributor.authorDehaene, Wim
dc.contributor.imecauthorYakimets, Dmitry
dc.contributor.imecauthorRadu, Iuliana
dc.contributor.imecauthorThean, Aaron
dc.contributor.imecauthorHeyns, Marc
dc.contributor.imecauthorDehaene, Wim
dc.contributor.orcidimecRadu, Iuliana::0000-0002-7230-7218
dc.date.accessioned2021-10-22T18:29:54Z
dc.date.available2021-10-22T18:29:54Z
dc.date.embargo9999-12-31
dc.date.issued2015
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24918
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7312439
dc.source.beginpage4051
dc.source.endpage4156
dc.source.issue12
dc.source.journalIEEE Transactions on Electron Devices
dc.source.volume62
dc.title

Benchmarking of MoS2 FETs with multigate Si-FET options for 5 nm and beyond

dc.typeJournal article
dspace.entity.typePublication
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