Publication:

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

Date

2020
Proceedings Paper
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dc.contributor.authorGupta, Anshul
dc.contributor.authorMertens, Hans
dc.contributor.authorTao, Zheng
dc.contributor.authorDemuynck, Steven
dc.contributor.authorBoemmels, Juergen
dc.contributor.authorArutchelvan, Goutham
dc.contributor.authorDevriendt, Katia
dc.contributor.authorVarela Pedreira, Olalla
dc.contributor.authorRitzenthaler, Romain
dc.contributor.authorWang, Shouhua
dc.contributor.authorRadisic, Dunja
dc.contributor.authorKenis, Karine
dc.contributor.authorTeugels, Lieve
dc.contributor.authorSebaai, Farid
dc.contributor.authorLorant, Christophe
dc.contributor.authorJourdan, Nicolas
dc.contributor.authorChan, BT
dc.contributor.authorZahedmanesh, Houman
dc.contributor.authorSubramanian, Sujith
dc.contributor.authorSchleicher, Filip
dc.contributor.imecauthorGupta, A.
dc.contributor.imecauthorMertens, H.
dc.contributor.imecauthorTao, Z.
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dc.date.accessioned2021-12-15T09:56:01Z
dc.date.available2021-11-02T15:59:09Z
dc.date.available2021-12-15T09:56:01Z
dc.date.issued2020
dc.identifier.eisbn978-1-7281-6460-1
dc.identifier.issn0743-1562
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/37742
dc.publisherIEEE
dc.source.conferenceIEEE Symposium on VLSI Technology and Circuits
dc.source.conferencedateJUN 15-19, 2020
dc.source.conferencelocationVirtual
dc.source.journalna
dc.source.numberofpages2
dc.title

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

dc.typeProceedings paper
dspace.entity.typePublication
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