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STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes

 
dc.contributor.authorGarcia-Redondo, F.
dc.contributor.authorRao, Siddharth
dc.contributor.authorGupta, Mohit
dc.contributor.authorPerumkunnil, Manu
dc.contributor.authorXiang, Yang
dc.contributor.authorAbdi, Dawit
dc.contributor.authorVan Beek, Simon
dc.contributor.authorCouet, Sebastien
dc.contributor.authorGarcia Bardon, Marie
dc.contributor.imecauthorRao, Siddharth
dc.contributor.imecauthorGupta, Mohit
dc.contributor.imecauthorPerumkunnil, Manu
dc.contributor.imecauthorXiang, Yang
dc.contributor.imecauthorAbdi, Dawit
dc.contributor.imecauthorVan Beek, Simon
dc.contributor.imecauthorCouet, Sebastien
dc.contributor.imecauthorGarcia Bardon, Marie
dc.contributor.orcidimecRao, Siddharth::0000-0001-6161-3052
dc.contributor.orcidimecGupta, Mohit::0000-0002-1924-1264
dc.contributor.orcidimecPerumkunnil, Manu::0000-0002-0029-6548
dc.contributor.orcidimecXiang, Yang::0000-0003-0091-6935
dc.contributor.orcidimecAbdi, Dawit::0000-0002-3598-8798
dc.contributor.orcidimecVan Beek, Simon::0000-0002-2499-4172
dc.contributor.orcidimecCouet, Sebastien::0000-0001-6436-9593
dc.contributor.orcidimecGarcia Bardon, Marie::0000-0001-5772-5406
dc.date.accessioned2024-05-06T14:52:43Z
dc.date.available2023-11-24T17:33:10Z
dc.date.available2024-05-06T14:52:43Z
dc.date.issued2023
dc.identifier.doi10.1109/ESSDERC59256.2023.10268481
dc.identifier.eisbn979-8-3503-0423-7
dc.identifier.issn1930-8876
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/43178
dc.publisherIEEE
dc.source.beginpage97
dc.source.conferenceIEEE 53rd European Solid-State Device Research Conference (ESSDERC)
dc.source.conferencedateSEP 11-14, 2023
dc.source.conferencelocationLisbon
dc.source.endpage100
dc.source.journalN/A
dc.source.numberofpages4
dc.title

STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes

dc.typeProceedings paper
dspace.entity.typePublication
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