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Challenges and Opportunities in D-Band Transmitter Architectures and Antenna Design, Integration, and Scalability for 6G Communications: A Brief Review

 
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0003-4025-2854
cris.virtualsource.departmentcea3c82b-d41f-431e-ab7e-117f91368f9c
cris.virtualsource.orcidcea3c82b-d41f-431e-ab7e-117f91368f9c
dc.contributor.authorAslam Shah Zaib
dc.contributor.authorWilcher, Alexander
dc.contributor.authorChatterjee, Baibhab
dc.contributor.authorYoon Yong-kyu
dc.contributor.authorArnold, David
dc.contributor.authorSinha, Siddhartha
dc.contributor.imecauthorSinha, Siddhartha
dc.contributor.orcidimecSinha, Siddhartha::0000-0003-4025-2854
dc.date.accessioned2025-04-15T04:20:29Z
dc.date.available2025-04-15T04:20:29Z
dc.date.issued2025
dc.description.abstractThis article reviews the current state-of-the-art (SOTA) key enabling technologies that pave the way for the advancement of scalable 6G antenna array systems for future communications. The focus is on the development of transmitter building blocks, considering the implementation of size, weight, area, and power (SWaP) constrained nodes. First, an overview of communication technologies from 1G to 6G is presented, followed by a discussion of key performance indicators and link budget analysis. To provide further insights into D-band (110-170 GHz) system design challenges, this review highlights the significance of 1) high-gain and high-linearity power amplifiers, 2) spectrally pure local oscillator (LO) signal sources, 3) high data rate modulator architectures, 4) scalable antenna array development, and 5) heterogeneous integration approaches. Furthermore, this article presents ongoing research and development on transmitter building blocks across various device fabrication technologies such as CMOS, BiCMOS, and III-V semiconductors. Special attention is given to the high data rate modulator architectures, which comprise 1) heterodyne, 2) homodyne, and 3) direct-digital modulators, followed by addressing the implementation challenges and opportunities in coherent and noncoherent modulation schemes within the context of SWaP-constrained scalable arrays for D-band. Additionally, this article reviews heterogeneous integration (HI) while focusing on chiplet designs for multifunctionality, low-loss packaging trends with thermal management solutions, chip-antenna interconnects featuring novel antenna technologies, and bottlenecks in mmWave/sub-THz measurements.
dc.description.wosFundingTextThis work was supported in part by the Defense Advanced Research Projects Agency (DARPA) and Army Research Office under Award W911NF-21-1-0360, in part by the NSF Convergence Accelerator Program under Grant ITE-2235978, and in part by the NSF Engine Program under Grant 2315320.
dc.identifier.doi10.1109/ACCESS.2025.3542771
dc.identifier.issn2169-3536
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/45535
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage33849
dc.source.endpage33873
dc.source.journalIEEE ACCESS
dc.source.numberofpages25
dc.source.volume13
dc.subject.keywordsPOWER-AMPLIFIER
dc.subject.keywordsOUTPUT POWER
dc.subject.keywords18 DBM
dc.subject.keywordsGHZ
dc.subject.keywordsTRANSCEIVER
dc.subject.keywordsRANGE
dc.subject.keywordsARRAY
dc.subject.keywordsPAE
dc.title

Challenges and Opportunities in D-Band Transmitter Architectures and Antenna Design, Integration, and Scalability for 6G Communications: A Brief Review

dc.typeJournal article
dspace.entity.typePublication
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