Publication:

Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs

Date

2021
Proceedings Paper
https://doi.org/10.1109/ISLPED52811.2021.9502475
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dc.contributor.authorAgnesina, Anthony
dc.contributor.authorBrunion, Moritz
dc.contributor.authorKim, Jinwoo
dc.contributor.authorGarcia-Ortiz, Alberto
dc.contributor.authorMilojevic, Dragomir
dc.contributor.authorCatthoor, Francky
dc.contributor.authorPerumkunnil, Manu
dc.contributor.authorLim, Sung Kyu
dc.contributor.imecauthorMilojevic, Dragomir
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.imecauthorPerumkunnil, Manu
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.accessioned2022-03-30T09:23:31Z
dc.date.available2021-11-02T15:55:22Z
dc.date.available2022-03-23T14:50:30Z
dc.date.available2022-03-30T09:23:31Z
dc.date.issued2021
dc.identifier.doi10.1109/ISLPED52811.2021.9502475
dc.identifier.eisbn978-1-6654-3922-0
dc.identifier.issn1533-4678
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/37447
dc.publisherIEEE
dc.source.conferenceIEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
dc.source.conferencedateJUL 26-28, 2021
dc.source.conferencelocationonline
dc.source.journalna
dc.source.numberofpages6
dc.title

Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs

dc.typeProceedings paper
dspace.entity.typePublication
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