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A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C

Date

2010
Proceedings Paper
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dc.contributor.authorCollaert, Nadine
dc.contributor.authorAoulaiche, Marc
dc.contributor.authorDe Wachter, Bart
dc.contributor.authorRakowski, Michal
dc.contributor.authorRedolfi, Augusto
dc.contributor.authorBrus, Stephan
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorAltimime, Laith
dc.contributor.authorJurczak, Gosia
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorDe Wachter, Bart
dc.contributor.imecauthorRakowski, Michal
dc.contributor.imecauthorRedolfi, Augusto
dc.contributor.imecauthorBrus, Stephan
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.contributor.orcidimecBrus, Stephan::0000-0003-3554-0640
dc.date.accessioned2021-10-18T15:40:26Z
dc.date.available2021-10-18T15:40:26Z
dc.date.embargo9999-12-31
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16899
dc.source.beginpage161
dc.source.conferenceIEEE Symposium on VLSI Technology
dc.source.conferencedate15/06/2010
dc.source.conferencelocationHonolulu, HI USA
dc.source.endpage162
dc.title

A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C

dc.typeProceedings paper
dspace.entity.typePublication
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