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Manufacturable processes for =32-nm-node CMOS enhancement by synchronous optimization of strain-engineered channel and external parasitic resistances
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Manufacturable processes for =32-nm-node CMOS enhancement by synchronous optimization of strain-engineered channel and external parasitic resistances
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Date
2008
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Noori, Atif
;
Balseanu, Mihaela
;
Boelen, Pieter
;
Cockburn, Andrew
;
Demuynck, Steven
;
Felch, Susan
;
Gandikota, Srinivas
;
Gelatos, jerry
;
Khandelwal, Amit
;
Kittl, Jorge
;
Lauwers, Anne
;
Lee, Wen-Chin
;
Lei, Jianxin
;
Mandrekar, Tushar
;
Schreutelkamp, Rob
;
Shah, Kavita
;
Thompson, Scott
;
Verheyen, Peter
;
Wang, Ching-Ya
;
Xia, Li-Qun
;
Arghavani, Reza
Journal
IEEE Transactions on Electron Devices
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2002
since deposited on 2021-10-17
1
last month
Acq. date: 2025-12-10
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Metrics
Views
2002
since deposited on 2021-10-17
1
last month
Acq. date: 2025-12-10
Citations