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Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies
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Authors
Huynh Bao, Trong
;
Yakimets, Dmitry
;
Ryckaert, Julien
;
Ciofi, Ivan
;
Baert, Rogier
;
Veloso, Anabela
;
Boemmels, Juergen
;
Collaert, Nadine
;
Roussel, Philippe
;
Demuynck, Steven
;
Raghavan, Praveen
;
Mercha, Abdelkarim
;
Tokei, Zsolt
;
Verkest, Diederik
;
Thean, Aaron
;
Wambacq, Piet
Conference
44th European Solid-State Device Research Conference - ESSDERC
Title
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies
Publication type
Proceedings paper
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