A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS

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Authors
Spagnolo, Annachiara; Verbruggen, Bob; D'amico, Stefano; Wambacq, Piet
Conference
40th European Solid-State Circuits Conference - ESSCIRC
Title
A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS
Publication type
Proceedings paper
Embargo date
9999-12-31
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