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A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS

dc.contributor.authorSpagnolo, Annachiara
dc.contributor.authorVerbruggen, Bob
dc.contributor.authorD'amico, Stefano
dc.contributor.authorWambacq, Piet
dc.date.accessioned2021-10-22T06:04:28Z
dc.date.available2021-10-22T06:04:28Z
dc.date.issued2014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24554
dc.sourceIIOimport
dc.titleA 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS
dc.typeProceedings paper
dc.contributor.imecauthorSpagnolo, Annachiara
dc.contributor.imecauthorWambacq, Piet
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage75
dc.source.endpage78
dc.source.conference40th European Solid-State Circuits Conference - ESSCIRC
dc.source.conferencedate22/09/2014
dc.source.conferencelocationVenice Italy
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDeails.jsp?arnumber=6942025
imec.availabilityPublished - open access


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