Publication:

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM

Date

2015

Proceedings Paper

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Files

31617.pdf 748.12 KB

Author(s)

Huynh Bao, Trong

;

Sakhare, Sushil

;

Ryckaert, Julien

;

Yakimets, Dmitry

;

Mercha, Abdelkarim

;

Verkest, Diederik

;

;

Statistics

1921 since deposited on 2021-10-22

Acq. date: 2026-02-25