Publication:

Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

Date

2018
Proceedings Paper
Simple item page Full metadata Statistics
Loading...
Thumbnail Image

Files

39497.pdf 925.52 KB

Author(s)

Sakhare, Sushil
;
Perumkunnil, Manu  
;
Huynh Bao, Trong
;
Rao, Siddharth  
;
Kim, Woojin  
;
Crotti, Davide  
;
Yasin, Farrukh  
;
Couet, Sebastien  
;
Swerts, Johan  
;
Kundu, Shreya  
;
Yakimets, Dmitry  
;
Baert, Rogier  
;
Oh, Hyungrock  
;
Spessot, Alessio  
;
Mocuta, Anda
;
Kar, Gouri Sankar  
;
Furnemont, Arnaud  

Journal

Abstract

Description

Statistics

Downloads

2 since deposited on 2021-10-26
Acq. date: 2026-10-06

Views

2002 since deposited on 2021-10-26
2last month
1last week
Acq. date: 2026-10-06

Citations

Statistics

Downloads

2 since deposited on 2021-10-26
Acq. date: 2026-10-06

Views

2002 since deposited on 2021-10-26
2last month
1last week
Acq. date: 2026-10-06

Citations