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Electrical and DLTS Characterization of Gate Interfaces in GaN-based Trench-gate semi-vertical MOS devices
Publication:
Electrical and DLTS Characterization of Gate Interfaces in GaN-based Trench-gate semi-vertical MOS devices
Date
2020
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Marek, Juraj
;
Mikoláek, Miroslav
;
Drobnŭ, Jakub
;
Kozarik, Jozef
;
Chvála, Ale
;
Geens, Karen
;
Borga, Matteo
;
Liang, Hu
;
You, Shuzhen
;
Decoutere, Stefaan
;
Stuchlíková, Lubica
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1969
since deposited on 2021-10-29
Acq. date: 2025-10-27
Citations
Metrics
Views
1969
since deposited on 2021-10-29
Acq. date: 2025-10-27
Citations