Stress in Silicon-Germanium Nanowires: Layout Dependence and Imperfect Source/Drain Epitaxial Stressors

Abstract

Stress simulations of Si0.5Ge0.5-channel nanowire transistors with typical 5 nm technology-node dimensions are performed to study the effect of layout on the channel stress generated by virtual substrates, by epitaxial mismatch from source/drain epitaxial layers, and by the sacrificial layers between the wires. Dependence of the stress on wire length originates from the wire cut, leading to elastic stress relaxation of the wire/sacrificial layer stack which is more pronounced toward the edge of the structure, and from reduced effectiveness of source/drain stressors at this edge. Consequently, large (>500 MPa) variations in channel stress are observed between long and short wires, between devices at different positions along the structure, as well as between the various wires within the same transistor for multiwire architectures. Besides layout dependence, this work also reports on the effect of nonideal, defective source/drain stressors on channel stress generation in nanowires. For nanowires, these defects may originate from merging of different epitaxial growth fronts coming from segments which start from different wires and the substrate. They can be classified into horizontal (between wires), vertical (between gates), and lateral defects (between neighboring structures). Stress simulations with air gaps at these locations allow estimating the impact of these defects for the case where there is no stress transfer across the defect planes. While horizontal and lateral defects lead to minimal (<10%) loss of channel stress, an imperfect interface between neighboring gates (vertical defects) is very detrimental and can lead to reversal of the stress sign as compared to perfect source/drain epi.