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Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures
Publication:
Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures
Date
2021
Journal article
https://doi.org/10.1109/TED.2021.3077349
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Silva, Vanessa C. P.
;
Perina, Welder F.
;
Martino, Joao A.
;
Simoen, Eddy
;
Veloso, Anabela
;
Agopian, Paula G. D.
Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
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1944
since deposited on 2022-03-07
Acq. date: 2025-10-29
Citations
Metrics
Views
1944
since deposited on 2022-03-07
Acq. date: 2025-10-29
Citations