First demonstration of ferroelectric Si:Hf0(2) based 3D FE-FET with trench architecture for dense non-volatile memory application

Abstract

A vertical 3D ferroelectric (FE) FET, fabricated with a trench-based architecture, has been demonstrated for the first time. Devices were fabricated on 300mm wafers across a wide range of channel dimensions. A memory window (MW) of 3V with an endurance of around 10(4) cycles and good retention were measured, thereby paving the way for multi-bit operation. This study lays the foundation for design and fabrication of ultra-dense, low power, non-volatile memory (NVM), which can succeed charge-trap based 3D NAND in the near future.