Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited)

Abstract

In this paper, we describe different design methodologies to bridge the gap between 3D and 2D Integrated Circuits in the Electronic Design Automation framework. An extended version of a Die-by-Die place and route flow for 3D systems is presented, focusing on the power management and timing optimization aspects. The corresponding sign-off methodologies to perform 3D power and timing optimization are developed using commercial tools. For both 3D-aware Multi-Die rail analysis and Static Timing Analysis, sample results on a test design example are included as means to validate the flows.