Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency

Abstract

Chiplet-based multi-die packages (a.k.a. 2.5D- and 3D-ICs) implement large amounts of inter-die interconnects with micro-bumps. To achieve uniform heights, these micro-bumps are typically placed in large rectangular or hexagonal arrays. These interconnects are subject to manufacturing defects. Traditional interconnect automatic test pattern generation (I-ATPG) methods, such as the True/Complement Algorithm [1], focus on hard open and short defects with test pattern count 2 x inverted right perpendicularlog(2)(k)inverted left perpendicular for k interconnects. However, the traditional I-ATPG methods indiscriminately cover short defects between all pairs of interconnects, including those for which shorts are unrealistic given their relative layout positions. In this paper we propose an effective and efficient interconnect test ((EITEST)-I-2). The proposed method improves the test effectiveness by covering both hard and weak variants of open and short defects. It improves the test efficiency by considering only shorts between adjacent interconnects. Because of this, it requires 8 x inverted right perpendicularlog(2)(4)inverted left perpendicular = 16 test patterns, thereby decoupling it from the dependency on k, which is large already today and only expected to grow.