A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology

Abstract

In this work, the challenge of the I/O development roadmap is discussed. Utilizing design and technology co-optimization (DTCO), a cost-effective circuit solution of a 1.8-V general-purpose I/O (GPIO) is proposed in this work. It is not only designed to have comparable performance with standard I/O cells but also better scalability adapting to the sub-3-nm gate-all-around (GAA) nanosheet (NS) technology. The proposed GPIO consists only of core transistors, so that an I/O transistor is not required. To tolerate I/O domain voltage of 1.8 V, the proposed GPIO is designed in the stacked architecture to be 3 $\times$ VDD tolerant. The proposed high-voltage tolerant level shifter with supplementary design achieves better technology scalability regarding performance. The dynamic gate bias (DGB) circuit can prevent gate-dielectric overstress in the output driver under static states. A new voltage-lowering technique has been proposed for receive mode (RX) and achieves better duty cycle and functionality of hysteresis. The functionality is demonstrated in a commercial 16-nm FinFET technology. Furthermore, the device-level reliability of stacked transistors is qualitatively evaluated by the proposed reconfigurable stacked-FET array. The circuit solution to the reliability concern induced by transient overstresses under transmit mode (TX) is proposed. In addition, the circuit-level reliability of the proposed GPIO is examined and shows comparability to the device-level measurement results. Finally, the area penalty and comparison of the conventional I/O buffer and the proposed GPIO has been analyzed, and the technology dependency of device reliability has been discussed.