Browsing by author "Groeseneken, Guido"
Now showing items 1-20 of 1153
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1/f noise analysis of replacement metal gate bulk p-type fin field effect transistor
Lee, Jae Woo; Cho, Moon Ju; Simoen, Eddy; Ritzenthaler, Romain; Togo, Mitsuhiro; Boccardi, Guillaume; Mitard, Jerome; Ragnarsson, Lars-Ake; Chiarella, Thomas; Veloso, Anabela; Horiguchi, Naoto; Thean, Aaron; Groeseneken, Guido (2013-03) -
15-band spectral envelope function formalism applied to broken gap tunnel field-effect transistors
Verreck, Devin; Van de Put, Maarten; Verhulst, Anne; Soree, Bart; Magnus, Wim; Dabral, Ashish; Thean, Aaron; Groeseneken, Guido (2015) -
200 V enhancement-mode p-GaN HEMTs fabricated on 200 mm GaN-on-SOI with trench isolation for monolithic integration
Li, Xiangdong; Van Hove, Marleen; Zhao, Ming; Geens, Karen; Lempinen, Vesa-Pekka; Sormunen, Jaakko; Stoffels, Steve; Groeseneken, Guido; Decoutere, Stefaan (2017) -
200 V enhancement-mode p-GaN HEMTs fabricated on 200 mm GaN-on-SOI with trench isolation for monolithic integration
Li, Xiangdong; Van Hove, Marleen; Zhao, Ming; Geens, Karen; Lempinen, Vesa-Pekka; Sormunen, Jaakko; Groeseneken, Guido; Decoutere, Stefaan (2017) -
2D rotational invariant multi subband schroedinger-poisson solver to model nanowire transistors
Sels, Dries; Soree, Bart; Groeseneken, Guido (2010) -
6Å EOT Si0.45Ge0.55 pMOSFET with optimized reliability (VDD=1V): Meeting the NBTI lifetime target at ultra-thin EOT
Franco, Jacopo; Kaczer, Ben; Eneman, Geert; Mitard, Jerome; Stesmans, Andre; Afanasiev, Valeri; Kauerauf, Thomas; Roussel, Philippe; Toledano-Luque, Maria; Cho, Moon Ju; Degraeve, Robin; Grasser, Tibor; Ragnarsson, Lars-Ake; Witters, Liesbeth; Tseng, Joshua; Takeoka, Shinji; Wang, Wei-E; Hoffmann, Thomas Y.; Groeseneken, Guido (2010) -
A 1.3dB NF CMOS LNA for GPS with 3kV HBM ESD-protection
Leroux, P.; Steyaert, M.; Vassilev, Vesselin; Groeseneken, Guido (2002-09) -
A 1.6dB NF CMOS LNA for GPS with 3kV HBM ESD-protection
Leroux, P.; Steyaert, M.; Vassilev, Vesselin; Groeseneken, Guido (2002) -
A 25ns/byte-programmable low-power SSI flash array with a new low-voltage erase scheme for embedded memory applications
Van Houdt, Jan; Haspeslagh, Luc; Wellekens, Dirk; Vanhorebeek, Guido; Groeseneken, Guido; Deferm, Ludo; Maes, Herman (1995) -
A 35nm diameter vertical silicon nanowire short-gate tunnelFET
Vandooren, Anne; Rooyackers, Rita; Leonelli, Daniele; Iacopi, Francesca; De Gendt, Stefan; Verhulst, Anne; Heyns, Marc; Kunnen, Eddy; Nguyen, Duy; Demand, Marc; Ong, Patrick; Lee, Willie; Moonens, Jos; Richard, Olivier; Vandenberghe, William; Groeseneken, Guido (2009) -
A 4.5 kV HBM, 300 V CDM, 1.2 kV HMM ESD protected DC-to-16.1 GHz wideband LNA in 90 nm CMOS
Linten, Dimitri; Thijs, Steven; Okushima, Mototsugu; Scholz, Mirko; Borremans, Jonathan; Dehan, Morin; Groeseneken, Guido (2009) -
A 5 V-Compatible Flash EEPROM Cell with Microsecond Programming Time for Embedded Memory Applications
Van Houdt, Jan; Wellekens, Dirk; Faraone, Lorenzo; Haspeslagh, Luc; Deferm, Ludo; Groeseneken, Guido; Maes, Herman (1994) -
A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits
Vassilev, Vesselin; Vaschenko, Vladislav; Jansen, Philippe; Choi, B.-J.; Concannon, An; Yang, J.-J,; Groeseneken, Guido; Mahadeva Iyer, Natarajan; Terbeek, Marcel; Hopper, Peter; Steyaert, Michiel; Maes, Herman (2004) -
A cautionary note when looking for a truly reconfigurable resistive RAM PUF
Chuang, Kent; Degraeve, Robin; Fantini, Andrea; Groeseneken, Guido; Linten, Dimitri; Verbauwhede, Ingrid (2018) -
A CMOS circuit for evaluating the NBTI over a wide frequency range
Fernandez-Garcia, Raul; Kaczer, Ben; Groeseneken, Guido (2009) -
A compact model for the grounded-gate nMOS behaviour under CDM ESD stress
Russ, Christian; Verhaege, Koen; Bock, Karlheinz; Roussel, Philippe; Groeseneken, Guido; Maes, Herman (1996) -
A compact model for the grounded-gate nMOS transistor behaviour under CDM ESD stress
Russ, Christian; Verhaege, Koen; Bock, Karlheinz; Roussel, Philippe; Groeseneken, Guido; Maes, Herman (1998) -
A compact MOSFET breakdown model for optimization of gate coupled ESD protection circuits
Vassilev, Vesselin; Groeseneken, Guido; Bock, Karlheinz; Maes, Herman (1999) -
A compact NBTI model for accurate analog integrated circuit reliability simulation
Maricau, Elie; Zhang, Leqi; Franco, Jacopo; Roussel, Philippe; Groeseneken, Guido; Gielen, Georges (2011) -
A comparative study of the oxide breakdown in short-channel nMOSFETs and pMOSFETs stressed in inversion and in accumulation regimes
Crupi, F.; Kaczer, Ben; Degraeve, Robin; De Keersgieter, An; Groeseneken, Guido (2003)