Browsing Articles by imec author "a99a71f690d199fc7614bea07dfe4c48891ae0dc"
Now showing items 1-20 of 52
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3D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability
Vandooren, Anne; Franco, Jacopo; Parvais, Bertrand; Wu, Zhicheng; Witters, Liesbeth; Walke, Amey; Li, Waikin; Peng, Lan; Deshpande, Veeresh Vidyadhar; Bufler, Fabian; Rassoul, Nouredine; Hellings, Geert; Jamieson, Geraldine; Inoue, Fumihiro; Verbinnen, Greet; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Tao, Zheng; Rosseel, Erik; Vanherle, Wendy; Hikavyy, Andriy; Chan, BT; Ritzenthaler, Romain; Besnard, Guillaume; Schwarzenbach, Walter; Gaudin, Gweltaz; Radu, Ionut; Nguyen, Bich-Yen; Waldron, Niamh; De Heyn, Vincent; Mocuta, Dan; Collaert, Nadine (2018-11) -
A 42 mW 200 fs-jitter 60 GHz sub-sampling PLL in 40 nm CMOS
Szortyka, Viki; Shi, Qixian; Raczkowski, Kuba; Parvais, Bertrand; Kuijk, Maarten; Wambacq, Piet (2015) -
A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability
Kaczer, Ben; Franco, Jacopo; Weckx, Pieter; Roussel, Philippe; Putcha, Vamsi; Bury, Erik; Simicic, Marko; Vaisman Chasin, Adrian; Linten, Dimitri; Parvais, Bertrand; Catthoor, Francky; Rzepa, Gerhard; Waltl, Michael; Grasser, Tibor (2018) -
Analog performance of GaN/AlGaN high-electron-mobility transistors
Bergamim, Luis Felipe de Oliveira; Parvais, Bertrand; Simoen, Eddy; de Andrade, Maria Gloria Cano (2021) -
Analysis of gate-metal resistance in CMOS-compatible RF GaN HEMTs
ElKashlan, Rana Y.; Rodriguez, Raul; Yadav, Sachin; Khaled, Ahmad; Peralagu, Uthayasankaran; Alian, AliReza; Waldron, Niamh; Zhao, Ming; Wambacq, Piet; Parvais, Bertrand; Collaert, Nadine (2020) -
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
Chiarella, Thomas; Witters, Liesbeth; Mercha, Abdelkarim; Kerner, Christoph; Rakowski, Michal; Ortolland, Claude; Ragnarsson, Lars-Ake; Parvais, Bertrand; De Keersgieter, An; Kubicek, Stefan; Redolfi, Augusto; Vrancken, Christa; Brus, Stephan; Lauwers, Anne; Absil, Philippe; Biesemans, Serge; Hoffmann, Thomas Y. (2010) -
Built-in sheet charge as an alternative to dopant pockets in tunnel field-effect transistors
Verreck, Devin; Verhulst, Anne; Xiang, Yang; Yakimets, Dmitry; El Kazzi, Salim; Parvais, Bertrand; Groeseneken, Guido; Collaert, Nadine; Mocuta, Anda (2018) -
Characterization and modeling of hot carrier degradation in N-channel gate-all-around nanowire FETs
Gupta, Charu; Gupta, Anshul; Tuli, Shikhar; Bury, Erik; Parvais, Bertrand; Dixit, Abhisek (2020) -
Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics
Xiang, Yang; Garcia Bardon, Marie; Kaczer, Ben; Alam, Md Nur Kutubul; Ragnarsson, Lars-Ake; Kaczmarek, Kuba; Parvais, Bertrand; Groeseneken, Guido; Van Houdt, Jan (2021) -
Comparison of temperature dependent carrier transport in FinFET and gate-all-Around nanowire FET
Kim, Soohyun; Kim, Jungchun; Jang, Doyoung; Ritzenthaler, Romain; Parvais, Bertrand; Mitard, Jerome; Mertens, Hans; Chiarella, Thomas; Horiguchi, Naoto; Lee, Jae Woo (2020) -
Cryogenic temperature DC-IV measurements and compact modeling of n-channel bulk FinFETs with 3-4 nm wide fins and 20 nm gate length for quantum computing applications
Gupta, Sumreti; Rathi, Aarti; Parvais, Bertrand; Dixit, Abhisek (2021) -
Deep submicron CMOS for millimeter wave power applications
Ferndahl, Mattias; Nemati, Hossein; Parvais, Bertrand; Zirath, Herbert; Decoutere, Stefaan (2008) -
Design and tuning of coupled-LC mm-wave subharmonically injection-locked oscillators
Mangraviti, Giovanni; Khalaf, Khaled; Parvais, Bertrand; Vaesen, Kristof; Szortyka, Viki; Vandersteen, Gerd; Wambacq, Piet (2015) -
Design of ultra-wideband low-noise amplifiers in 45nm CMOS technology: comparison between planar bulk and SOI FinFET devices
Ponton, Davide; Palestri, P.; Esseni, D.; Selmi, L.; Tiebout, M.; Parvais, Bertrand; Siprak, D.; Knoblinger, G. (2009) -
Determination and validation of new nonlinear FinFET model based on lookup ables
Crupi, Giovanni; Schreurs, Dominique; Xiao, Dongping; Caddemi, Alina; Parvais, Bertrand; Mercha, Abdelkarim; Decoutere, Stefaan (2007) -
Double-gate FinFETs as a CMOS technology downscaling option: an RF perspective
Nuttinck, Sebastien; Parvais, Bertrand; Curatola, Gilberto; Mercha, Abdelkarim (2007-02) -
Efficient Modeling of Charge Trapping a Cryogenic Temperatures-Part II: Experimental
Michl, Jakob; Grill, Alexander; Waldhoer, Dominic; Goes, Wolfgang; Kaczer, Ben; Linten, Dimitri; Parvais, Bertrand; Govoreanu, Bogdan; Radu, Iuliana; Grasser, Tibor; Waltl, Michael (2021) -
Efficient Modeling of Charge Trapping at Cryogenic Temperatures-Part I: Theory
Michl, Jakob; Grill, Alexander; Waldhoer, Dominic; Goes, Wolfgang; Kaczer, Ben; Linten, Dimitri; Parvais, Bertrand; Govoreanu, Bogdan; Radu, Iuliana; Waltl, Michael; Grasser, Tibor (2021) -
ESD HBM Discharge Model in RF GaN-on-Si (MIS)HEMTs
Wu, Wei-Min; Ker, Ming-Dou; Chen, Shih-Hung; Sibaja-Hernandez, Arturo; Yadav, Sachin; Peralagu, Uthayasankaran; Yu, Hao; Alian, AliReza; Putcha, Vamsi; Parvais, Bertrand; Collaert, Nadine; Groeseneken, Guido (2022-01-25) -
Experimental evaluation of self-heating and analog/RF FOM in GAA-nanowire FETs
Singh, Ramendra; Aditya, Kritika; Veloso, Anabela; Parvais, Bertrand; Dixit, Abhishek (2019)