2025 IEEE 75TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC
Abstract
Wafer bonding is becoming a key enabling technology for advanced semiconductor devices, and as pitch scaling continues, precise wafer-to-wafer alignment becomes increasingly critical. Variations in incoming wafer shape can significantly impact bonding overlay. In this study, we investigate the bonding of wafers with saddle shape, a deformation commonly observed in 3D NAND wafers. Our findings show that bonding errors are much higher for these wafers compared to those with more symmetric shapes, with a significant portion of the overlay attributed to asymmetric scaling. Enhancing asymmetric scaling compensation is crucial for reducing bonding overlay, benefiting not only 3D NAND-to-logic bonding but also other applications involving wafers with minor shape asymmetries. A method for reducing asymmetry utilizing the top chuck control is presented, along with a discussion of its limitations. Additionally, we discuss the measurement results of backside post-thinning lithography overlay with higher order correction, which is crucial for applications requiring highly accurate backside patterning alignment.