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High yield sub-0.1μm² 6T-SRAM Cells, featuring high-k/metal-gate Finfet devices, double gate patterning, a novel Fin etch strategy, full-field EUV lithography and optimized junction design & layout
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High yield sub-0.1μm² 6T-SRAM Cells, featuring high-k/metal-gate Finfet devices, double gate patterning, a novel Fin etch strategy, full-field EUV lithography and optimized junction design & layout
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