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High yield sub-0.1μm² 6T-SRAM Cells, featuring high-k/metal-gate Finfet devices, double gate patterning, a novel Fin etch strategy, full-field EUV lithography and optimized junction design & layout
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High yield sub-0.1μm² 6T-SRAM Cells, featuring high-k/metal-gate Finfet devices, double gate patterning, a novel Fin etch strategy, full-field EUV lithography and optimized junction design & layout
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Date
2010
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Horiguchi, Naoto
;
Demuynck, Steven
;
Ercken, Monique
;
Locorotondo, Sabrina
;
Lazzarino, Frederic
;
Altamirano Sanchez, Efrain
;
Huffman, Craig
;
Brus, Stephan
;
Demand, Marc
;
Struyf, Herbert
;
De Backer, Johan
;
Hermans, Jan
;
Delvaux, Christie
;
Vandeweyer, Tom
;
Baerts, Christina
;
Mannaert, Geert
;
Truffert, Vincent
;
Verluijs, j
;
Alaerts, Wilfried
;
Dekkers, Harold
;
Ong, Patrick
;
Heylen, Nancy
;
Kellens, Kristof
;
Volders, Henny
;
Hikavyy, Andriy
;
Vrancken, Christa
;
Rakowski, Michal
;
Verhaegen, Staf
;
Vandenberghe, Geert
;
Beyer, Gerald
;
Lauwers, Anne
;
Absil, Philippe
;
Hoffmann, Thomas Y.
;
Ronse, Kurt
;
Biesemans, Serge
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1
since deposited on 2021-10-18
Acq. date: 2025-12-10
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1967
since deposited on 2021-10-18
Acq. date: 2025-12-10
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Metrics
Downloads
1
since deposited on 2021-10-18
Acq. date: 2025-12-10
Views
1967
since deposited on 2021-10-18
Acq. date: 2025-12-10
Citations