Browsing by Author "Chava, Bharani"
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Publication Architectural strategies in standard-cell design for the 7 nm and beyond technology node
Journal article2016, Journal of Micro/Nanolithography MEMS and MOEMS, (15) 1, p.13507Publication Backside power delivery as a scaling knob for future systems
Meeting abstract2019, Design-Process-Technology Co-optimization for Manufacturability XIII, 25/02/2019, p.1096205Publication Design technology co-optimization for a robust 10nm solution for logic design and Sram
Proceedings paper2014, Design-Process-Technology Co-Optimization for Manufacturability VIII, 25/02/2014, p.90530QPublication Design technology co-optimization for N10
Proceedings paper2014, IEEE Proceedings of the Custom Integrated Circuits Conference - CICC, 15/09/2014, p.1-8Publication DTCO exploration for efficient standard cell power rails
Proceedings paper2018, Design-Process-Technology Co-optimization for Manufacturability XII, 25/02/2018, p.105880BPublication Extending the roadmap beyond 3nm through system scaling boosters: A case study on buried power rail and backside power delivery
Proceedings paper2019, 2019 Electron Devices Technology and Manufacturing Conference (EDTM), 12/03/2019, p.50Publication High-aspect-ratio ruthenium lnes for buried power rail
Proceedings paper2018, IEEE International Interconnect Technology Conference - IITC, 4/06/2018, p.4-6Publication Impact of a SADP flow on the design and process for N10/N7 layers
Proceedings paper2015, Design-Process-Technology Co-optimization for Manufacturability IX, 7/02/2015, p.942709Publication Low track height standard cell design in iN7 using scaling boosters
Proceedings paper2017, Design-Process-Technology Co-optimization for Manufacturability XI, 26/02/2017, p.101480YPublication Power Delivery Network (PDN) modeling for backside-PDN configurations with buried power rails and uTSVs
Journal article2020, IEEE Transactions on Electron Devices, (67) 1, p.11-17Publication SRAM with buried power distribution to improve write margin and performance in advanced technology nodes
Journal article2019, IEEE Electron Device Letters, (40) 8, p.1261-1274Publication Standard cell design in N7: EUV vs. immersion
; ; ; ; Proceedings paper2015, Design-Process-Technology Co-Optimization for Manufacturability IV, 22/02/2015, p.94270EPublication TEASE: A systematic analysis framework for early evaluation of FinFET-based advanced technology nodes
Proceedings paper2013, 50th ACM/EDAC/IEEE Design Automation Conference - DAC, 2/06/2013