Browsing by Author "Chi, Chun-Chuan"
Now showing 1 - 10 of 10
- Results per page
- Sort Options
Publication 3D DfT architecture for pre-bond and post-bond testing
Proceedings paper2010-11, IEEE International 3D Systems Integration Conference - 3DIC, 16/11/2010, p.1Publication A DfT architecture for 3D-SICs based on a standardizable die wrapper
Journal article2012-02, Journal of Electronic Testing - Theory and Applications, (28) 1, p.73-92Publication A standardizable 3D DfT architecture
Oral presentation2010, IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits - 3D-TESTPublication An IEEE Std 1500-based 3D design-for-test architecture
Proceedings paper2010-11, IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits - 3D-TEST, 4/11/2010Publication DfT architecture for 3D-SICs with multiple towers
Proceedings paper2011-05, IEEE European Test Symposium - ETS, 23/05/2011, p.51-56Publication DfT architecture for multi-tower 3D-SICs
Oral presentation2011, DATE'11 Friday Workshop on "3D Integration"Publication Low-cost post-bond testing of 3D-ICs containing a passive silicon interposer base
Journal article2014-11, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (22) 11, p.2388-2401Publication Multi-visit TAMs to reduce the post-bond test length of 2.5D-SICs with a passive silicon interposer base
Proceedings paper2011-11, IEEE Asian Test Symposium - ATS, 21/11/2011Publication Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base
Proceedings paper2011-09, IEEE International Test Conference - ITC, 20/09/2011, p.1-10