Browsing by Author "Cho, Jong Hoon"
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Publication An analytical compact model for estimation of stress in multiple through-silicon via configurations
Proceedings paper2011, Design, Automation and Test in Europe Conference - DATE, 14/03/2011, p.505-506Publication Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances
Proceedings paper2010, IEEE International Electron Devices Meeting - IEDM, 6/12/2010, p.26-29Publication Impact of thinning and through silicon via proximity on high-k / metal gate first CMOS performance
Proceedings paper2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.109-110