Browsing by Author "Clark, William"
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Publication A million wafer, virtual fabrication approach to determine process capability requirements for an industry-standard 5nm BEOL two-level metal flow
Proceedings paper2016, International Conference on Simulation of Semiconductor Processes and Devices - SISPAD, 6/09/2016, p.43-46Publication Feasibility study of fully self aligned vias for 5nm node BEOL
Proceedings paper2017, IEEE International Interconnect Technology Conference - IITC, 16/05/2017, p.1-4Publication Modeling of tone inversion process flow for N5 interconnect to characterize block tip to tip
Proceedings paper2017, IEEE International Interconnect Technology Conference - IITC, 16/05/2017, p.1-3Publication RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs
Proceedings paper2015, Symposium on VLSI Technology, 15/06/2015, p.148-149Publication Self-aligned-quadruple-patterning for N7/N5 silicon fins
Proceedings paper2016, SPIE Lithography Symposium Advanced Etch Technology for Nanopatterning V, 22/02/2016, p.DOI: 10.1117/2.1Publication Toward sub-20nm pitch Fin patterning and integration with DSA
Proceedings paper2016, Advances in Patterning Materials and Processes XXXIII, 22/02/2016, p.97790R