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Browsing by Author "Duffy, R."

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    CMOS scaling beyond the 90 nm CMOS technology node: shallow junction and integration challenges

    Dachs, Charles
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    Surdeanu, Radu
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    Pawlak, Bartek  
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    Doornbos, Gerben  
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    Duffy, R.
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    Heringa, Anco
    Proceedings paper
    2003, Ultra Shallow Junctions. 7th Int. Worksh. Fabrication, Characterization and Modeling of Ultra Shallow Doping Profiles in Semic., 27/04/2003, p.15-22
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    Conformal doping for FINFET's: a fabrication and metrology challenge

    Vandervorst, Wilfried  
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    Everaert, Jean-Luc
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    Rosseel, Erik  
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    Jurczak, Gosia  
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    Hoffmann, Thomas Y.
    Oral presentation
    2008, Stanford & Tohoku University Joint Open Workshop on 3D Transistor and its Applications
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    Junction architecture for planar devices

    Pawlak, Bartek  
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    Duffy, R.
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    Hoffmann, Thomas Y.
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    Severi, Simone  
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    Felch, S.B.
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    Eyben, Pierre  
    Proceedings paper
    2007, Advanced Gate Stack, Source/Drain and Channel Engineering for Si-Based CMOS 3: New Materials, Processes and Equipment, 6/05/2007, p.351-364
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    Quantitative prediction of junction leakage in bulk-technology CMOS devices

    Duffy, R.
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    Heringa, A.
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    Venezia, V.C.
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    Loo, Josine
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    Verheijen, M.A.
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    Hopstaken, M.J.P.
    Journal article
    2010, Solid-State Electronics, (54) 3, p.243-251

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