Browsing by Author "Harada, N."
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Publication 12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices
; ; ; ; Huynh Bao, TrongProceedings paper2019, 2019 Symposium on VLSI Technology, 9/06/2019, p.T15-1Publication DTCO and TCAD for a 12 layer-EUV ultra-scaled surrounding gate transistor 6T-SRAM
Proceedings paper2018, 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 24/09/2018, p.45-48Publication Interconnects for scaled SRAM with vertical Surrounded Gate Transistors (SGT)
Proceedings paper2019, IEEE International Interconnect Technology Conference (IITC 2019) and Materials for Advanced Metallization Conference (MAM 2019), 3/06/2019, p.2.5