Browsing by Author "Liu, Hsiao-Hsuan"

CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark

Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes

Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes

Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access

Energy-efficient In-Memory Address Calculation

Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect

Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes

Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus