Browsing by Author "Lu, J.P."
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Publication Analysis of the pre-epi bake conditions on the defect creation in recessed Si1-xGex S/D junctions
Proceedings paper2007, Analytical and Diagnostic Techniques for Semiconductor Materials, Devices, and Processes 7, 7/10/2007, p.47-53Publication Factors influencing the leakage current in embedded SiGe source/drain junctions
Journal article2008, IEEE Transactions on Electron Devices, (55) 3, p.925-930Publication Influence of the highly-doped drain implantation and the window size on defect creation in p/n Si1-xGex source/drain junctions
Publication Relaxation induced excess leakage current in recessed Si1-xGex source/drain junctions
Proceedings paper2007, Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS 3: New Materials, Processes and Equipment, 6/05/2007, p.389-396