Browsing by Author "Maes, Herman"
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Publication A 180nm secondary electron injection flash device
Proceedings paper2001, IEEE Non-Volatile Semiconductor Memory Workshop, 12/08/2001, p.62-63Publication A 1Mbit HIMOS® flash memory embedded in a 0.35μm CMOS process
Oral presentation2000, 17th IEEE Nonvolatile Semiconductor Memory Workshop; 13-17 February 2000; Monterey, Ca, USA.Publication A 25ns/byte-programmable low-power SSI flash array with a new low-voltage erase scheme for embedded memory applications
Proceedings paper1995, 14th IEEE Nonvolatile Semiconductor Memory Workshop, 13/08/1995, p.2.2Publication A 5 V-Compatible Flash EEPROM Cell with Microsecond Programming Time for Embedded Memory Applications
Journal article1994, IEEE Trans. Components, Packaging, and Manufacturing Techn. Part A, (17) 3, p.380-389Publication A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits
Publication A CMOS DC voltage doubler with nonoverlapping switching control
Journal article2001, IEICE Trans. Electronics, (E84C) 2, p.274-277Publication A compact model for the grounded-gate nMOS behaviour under CDM ESD stress
Proceedings paper1996, Proceedings of 18th Annual Electrical Overstress/Electrostatic Discharge Symposium, 10/09/1996, p.302-315Publication A compact model for the grounded-gate nMOS transistor behaviour under CDM ESD stress
Journal article1998, Journal of Electrostatics, (42) 4, p.351-381Publication A compact MOSFET breakdown model for optimization of gate coupled ESD protection circuits
Proceedings paper1999, ESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference; 13-15 September 1999; Leuven, Belgium., p.600-603Publication A comparison of extraction techniques for threshold voltage mismatch
Proceedings paper2002, International Conference on Microelectronic Test Structures, 8/04/2002, p.235-240Publication A comprehensive study of boron and carbon diffusion models in SiGeC heterojunction bipolar transistors
Journal article2005, Journal of Applied Physics, (98) 6, p.063530-1-063530-9Publication A consistent model for the SANOS programming operation
Proceedings paper2007, 22nd Non-Voltaile Semiconductor Memory Workshop - NVSMW, 27/08/2007, p.96-97Publication A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides
Proceedings paper1995, International Electron Devices Meeting. Technical Digest, 10/12/1995, p.863-866Publication A constant reference bit-line voltage data sensing technique without reference cell for 1T1C FeRAMs
Publication A fast and simple methodology for lifetime prediction of ultra-thin oxides
Proceedings paper1999, Proceedings of the International Reliability Physics Symposium; March 1999; San Diego, Ca, USA., p.381-388Publication A ferroelectric capacitor model accounting for the switching kinetics and polarization relaxation
Meeting abstract2001, 13th International Symposium on Integrated Ferroelectrics - ISIF, 11/03/2001, p.50Publication A flash memory technology with quasi-virtual ground array for low-cost embedded applications
Journal article2001, IEEE Journal of Solid-State Circuits, (36) 6, p.969-978Publication A low voltage, high performance 0.35 μm embedded flash EEPROM cell technology
Proceedings paper1998, 16th Nonvolatile Semiconductor Memory Workshop, 2/08/1998, p.106-108Publication A method to interpret micro-Raman experiments made to measure nonuniform stresses: application to local oxidation of silicon structures
Publication A new analytic model for the description of the intrinsic oxide breakdown statistics of ultra-thin oxides
Journal article1996, Microelectronics and Reliability, 36, p.1639-1642