Browsing by Author "Maes, J. W."
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Publication Backside Power Delivery With Relaxed Overlay for Backside Patterning Using Extreme Wafer Thinning and Molybdenum-Filled Slit Nano Through Silicon Vias
Journal article2024, IEEE TRANSACTIONS ON ELECTRON DEVICES, (71) 12, p.7963-7969Publication Multi-Vt Gate Stack Technologies for Nanosheet and CFET Devices
Proceedings paper2024, IEEE Silicon Nanoelectronics Workshop (SNW) / Symposium on VLSI Technology and Circuits, 2024-06-15, p.47-48Publication Pure-Metal Replacement Gate for Reliable 30 nm Pitch Scaled 3D NAND Flash
; ; ; ; ; Maes, J. W.Proceedings paper2024, International Memory Workshop (IMW), 2024-05-12Publication Selective ALD Mo Deposition in 10nm Contacts
Proceedings paper2023, IEEE International Interconnect Technology Conference (IITC) / IEEE Materials for Advanced Metallization Conference (MAM), MAY 22-25, 2023