Browsing by Author "Mahadeva Iyer, Natarajan"
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Publication A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS
Proceedings paper2004-09, Proceedings of the 30th European Solid-State Circuits - ESSCIRC, 20/09/2004, p.291-294Publication A 6.5-kV ESD protected 3-5-GHz ultra-wideband BiCMOS low noise amplifier using interstage gain roll-off compensation
Proceedings paper2005-09, Proceedings of the IEEE International Conference on Ultra-Wideband, 5/09/2005, p.525-529Publication A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits
Publication A low cost 90nm RF-CMOS platform for record RF circuit performance
Proceedings paper2005-06, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.60-61Publication A novel method for guard ring efficiency assessment and its application for esd protection design and optimization
Publication A plug-and-play wideband RF circuit ESD protection methodology: T-diodes
Journal article2009, Microelectronics Reliability, (49) 12, p.1440-1446Publication A traceable method for the arc-free characterization and modeling of CDM testers and pulse metrology chains
Publication Advanced modeling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies
Proceedings paper2004, Electrical Overstress / Electrostatic Discharge Symposium Proceedings, 19/09/2004, p.2.B.1Publication An integrated 5 GHz low-noise amplifier with 5.5 kV HBM ESD protection in 90nm RF CMOS
Proceedings paper2005-06, Symposium on VLSI Circuits Technical Digest, 16/06/2005, p.86-89Publication Class 3 HBM and class C MM ESD protected 5.5 GHz LNA in 90 nm RF CMOS using above-IC inductors
Proceedings paper2005, Proceedings 27th Annual EOS/ESD Symposium, 11/09/2005, p.1A.4Publication Co-design methodology to provide high esd protection levels in the advanced rf circuits
; ; ; Leroux, P.Proceedings paper2003-09, Proceedings EOS/ESD Symposium, 21/09/2003, p.195-203Publication Contributions to standardization of transmission line pulse testing methodology
Proceedings paper2001, Electrical Overstress/Electrostratic Discharge Syymposium Proceedings - EOS/ESD, p.461-467Publication Design-driven optimisation of a 90 nm RF CMOS process by use of elevated source/drain
Proceedings paper2003-09, 33rd European Solid-State Devices Research Conference - ESSDERC, 16/09/2003, p.43-46Publication Effect of the n+-sinker in self-triggered bipolar ESD protection structures
Proceedings paper2002, Proceedings 24th EOS/ESD Symposium, 6/10/2002, p.274-280Publication Electrostatic discharge (ESD) protection for sub-90nm RFCMOS designs
Oral presentation2005, Workshop and IEEE EDS Mini-Colloquium on NAnometer CMOS Technology - WIMNACTPublication Electrostatic discharges protection for emerging technologies and RF applications
Proceedings paper2005, Marie-Curie Conference "Making Europe more attractive for researchers", 28/09/2005Publication ESD protection challenges in RFCMOS circuits - an overview
Oral presentation2004, IEEE International Symposium on Microwaves - ISMPublication ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS implementation concepts, constraints and solutions
Proceedings paper2004, Electrical Overstress / Electrostatic Discharge Symposium Proceedings, 19/09/2004, p.1.B.2Publication ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS implementation concepts, constraints and solutions
Proceedings paper2005-11, RCJ Symposium, 10/11/2005, p.97-106Publication ESD reliability challenges for RF/mixed signal design and processing