Browsing by Author "Nouri, Faran"
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Publication A systematic study of trade-offs in engineering a locally strained pMOSFET
Proceedings paper2004, Technical Digest International Electron Devices Meeting - IEDM, 13/12/2004, p.1055-1058Publication Exploring the limits of stress-enhanced hole mobility
Journal article2005-09, IEEE Electron Device Letters, (26) 9, p.652-654Publication Further optimization of plasma nitridation of ultra-thin oxides for 65 nm node MOSFETS
Proceedings paper2004, Advanced Short-Time Thermal Processing for Si-based CMOS Devies II, 9/05/2004, p.236-243Publication Impact of recessed S/D SiGe integration parameters on device performance
Proceedings paper2005, Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 15/05/2005, p.515-522Publication Integration of a recessed SiGe Source/Drain into a PMOS transistor
Proceedings paper2005, 5th International SEMI-ECS Semiconductor Technology Conference, 15/03/2005Publication Layout impact on the performance of a locally strained PMOSFET
Proceedings paper2005, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.22-23Publication The impact of layout on stress-enhanced transistor performance
Proceedings paper2005, Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices - SISPAD, 1/09/2005, p.143-146