Browsing by Author "Pavanello, M.A."
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Publication A study on the self-heating effect in deep submicrometer partially depleted SOI MOSFET at low temperature
Proceedings paper2003, Proceedings of the 18th Symposium on Microelectronics Technology and Devices - SBMICRO, 8/09/2003, p.112-119Publication An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices
Journal article2012, Microelectronics Reliability, (52) 3, p.519-524Publication An analytical model for the non-linearity of triple gate SOI MOSFETs
Proceedings paper2011, Advanced Semiconductor-on-Insulator Technology and Related Physics 15, 1/05/2011, p.189-194Publication Analog operation of uniaxially and biaxially strained FD SOI nMOSFETs at cryogenic temperatures
Proceedings paper2008, EUROSOI Workshop Proceedings: 4th Workshop of the Thematic Network on Silicon-on-Insulator Technology, Devices and Circuits, 23/01/2008, p.77-78Publication Analog operation of uniaxially strained FD SOI nMOSFETs in cryogenic temperatures
Proceedings paper2007, IEEE International SOI Conference, 1/10/2007, p.45-46Publication Analog performance of standard and strained triple-gate nFINFETS
Journal article2008, Solid-State Electronics, (52) 12, p.1904-1909Publication Analysis of deep submicron bulk and fully depleted SOI nMOSFET analog operation at cryogenic temperatures
Proceedings paper2005, Silicon-on-Insulator Technology and Devices XII: Proceedings of the International Symposium, 15/05/2005, p.289-294Publication Analysis of halo implant influence on the self-heating and self-heating enhanced impact ionization on 0.13μm floating-body partially-depleted SOI MOSFET at low temperature
Proceedings paper2003, Silicon-on-Insulator Technology and Devices XI, 28/04/2003, p.389-394Publication Analysis of standard and strained FinFET operation in source-follower buffer configuration
Proceedings paper2009, 5th EUROSOI Workshop, 19/01/2009, p.59-60Publication Analysis of temperature-induced saturation threshold voltage degradation in deep-submicron ultrathin SOI MOSFETs
Journal article2005, IEEE Trans. Electron Devices, (52) 10, p.2236-2242Publication Comparison between 0.13 μm partially depleted silicon-on-insulator technology with floating body operation at 300 K and 90 K
Proceedings paper2002, Proceedings of the 17th International Symposium on Microelectronics Technology and Devices - SBMICRO, 9/09/2002, p.205-212Publication Comparison between bulk and floating body partially depleted SOI nMOSFETs for high frequency analog applications operating from 300 K down to 90 K
Proceedings paper2005, Proceedings SBMicro: 20th Symposium on Microelectronics Technology and Devices, 5/09/2005, p.464-474Publication Comparison between drain induced barrier lowering in partially and fully depleted 0.13 μm SOI nMOSFETs in low temperature operation
Proceedings paper2004, Proceedings WOLTE-6 - 6th European Workshop on Low Temperature Electronics, 23/06/2004, p.105-111Publication Cryogenic operation of FinFETs aiming at analog applications
Journal article2009, Cryogenics, 49, p.590-594Publication Cryogenic operation of FinFETs for space applications
Oral presentation2008, 8th International Workshop on Low Temperature Electronics - WOLTEPublication Effect of biaxial mechanical strain in the analog operation of fully depleted SOI transistors as a function of temperature
Meeting abstract2011, 219th ECS Meeting, 1/05/2011, p.1432Publication Effect of substrate rotation on the analog performance of triple-gate FinFETs
Proceedings paper2009, IEEE SOI conference, 5/10/2009Publication Evaluation of triple-gate FinFETs with SiO2-HfO2-TiN gate stack under analog operation
Journal article2007, Solid-State Electronics, (51) 2, p.285-291Publication Fin width influence on the harmonic distortion of standard and strained FinFETs operating in saturation
Proceedings paper2009, 24th Symposium on Microelectronics Technology and Devices - SBMicro, 31/08/2009, p.613-620Publication Halo effects on 0.13 μm floating-body partially depleted SOI n-MOSFETs in low temperature operation
Proceedings paper2004, Low temperature Electronis and Low Temperature Cofired Ceramic Based Electronic Devices, 11/10/2003, p.3-15