Browsing by Author "Poliakov, Pavel"
- Results per page
- Sort Options
Publication Bridging lithography processes with NAND flash ECC complexity
Proceedings paper2011-06, 3rd International Memory Workshop - IMW, 22/05/2011, p.161-164Publication Circuit design for bas compatibility in novel FinFET-based floating body RAM
Journal article2010, IEEE Transactions on Circuits and Systems II: Express Briefs, (57) 3, p.183-187Publication Circuit design for bias compatibility investigation of bulk FinFET based floating body RAM
Proceedings paper2009, IEEE Workshop on Memory Technology, Design and Testing, 31/08/2009Publication Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness
Journal article2011-05, Microelectronics Reliability, (51) 5, p.919-924Publication Impact of EUV lithography line edge roughness on 16 nm memory generation
Oral presentation2011, 55th International conference on Electron, Ion and Photon Beam Technology and Nanofabrication - EIPBNPublication Impact of line edge roughness on cell-to-cell coupling variability in NAND flash arrays
Proceedings paper2010-03, 11th International Conference on Ultimate Integration on Silicon - ULIS, 17/02/2010, p.41-44Publication Induced variability of cell-to-cell interference by line edge roughness in nand flash arrays
Journal article2012, IEEE Electron Device Letters, (33) 2, p.164-166Publication Linking EUV lithography line edge roughness and 16 nm NAND memory performance
Journal article2012, Microelectronic Engineering, (98) 10, p.24-28Publication Modeling and exploration of novel non-volatile memory technologies
Poliakov, PavelPHD thesis2012-09Publication Spacer-defined EUV lithography reducing variability of 12nm NAND Flash memories
Proceedings paper2012, 4th IEEE International Memory Workshop - IMW, 20/06/2012, p.33-36Publication Trades-off between line edge roughness and error-correcting codes requirements for NAND Flash Memories
Journal article2012, Microelectronics Reliability, (52) 3, p.525-529Publication Variability aware modeling of SoCs: from device variations to manufactured system yield
Proceedings paper2009, International Symposium on Quality Electronic Design, 16/03/2009