Browsing by Author "Serbulova, Kateryna"
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Publication CMOS Scaling by Nanosheet Device Architectures and Backside Engineering
Proceedings paper2024, International VLSI Symposium on Technology, Systems and Applications (VLSI), APR 22-25, 2024Publication ESD protection diodes in sub-5nm gate-all-around nanosheet technologies
; ; ; ; ; Meeting abstract2020, 2020 42nd EOS/ESD Symposium, 13/09/2020Publication ESD Robustness of Germanium Photodetectors in Advanced Silicon Photonics Technology
Proceedings paper2024, 46th Annual Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), SEP 16-18, 2024Publication Evaluating latchup (LU) risk in advanced CMOS technologies
Meeting abstract2020, International ESD Workshop (IEW), 4/05/2020, p.C1Publication Impact of Backside Power Delivery Network with Buried Power Rails on Latch-up Immunity in DTCO/STCO
Proceedings paper2023, 45th Annual Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium, OCT 02-04, 2023Publication Impact of Sub-mu m Wafer Thinning on Latch-up Risk in STCO Scaling Era
Publication Impact of Sub-µm Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling Era
Journal article2024, IEEE TRANSACTIONS ON ELECTRON DEVICES, (71) 4, p.2278-2283Publication Insight into Latchup Risk in 28nm Planar Bulk Technology for Quantum Computing Applications
; ; ; ; Publication TCAD study of latch-up sensitivity to wafer thinning below 500 nm
Proceedings paper2021, 44th International Semiconductor Conference (CAS), OCT 06-08, 2021, p.121-124