Browsing by Author "Soussou, Assawer"
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Publication Evaluation of the impact of source/drain epi implementation on logic performance using combined process and circuit simulation
Proceedings paper2020, International Conference on Solid State Devices and Materials - SSDM 2020, 27/09/2020, p.A-5-03Publication Introducing 2D-FETs in Device Scaling Roadmap using DTCO
Proceedings paper2020, IEEE International Electron Devices Meeting (IEDM), DEC 12-18, 2020Publication Process sensitivity analysis for EPE optimization of MP18 SALELE BEOL patterning
Proceedings paper2025, 2025 Conference on Metrology Inspection and Process Control-Annual, FEB 24-28, 2025, p.1Publication Self-aligned fin cut last patterning scheme for fin arrays of 24nm pitch and beyond
Oral presentation2018, SPIE Advanced LithographyPublication Self-aligned fin cut last patterning scheme for fin arrays of 24nm pitch and beyond
Proceedings paper2019, Advances in Patterning Materials and Processes XXXVI, 24/02/2019, p.109600N