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Browsing by Author "Stanojevic, Z."

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    A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics

    Schanovsky, F.
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    Rzepa, G.
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    Stanojevic, Z.
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    Kernstock, C.
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    Baumgartner, O.
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    Karner, M.
    Proceedings paper
    2021, IEEE International Memory Workshop (IMW), MAY 16-19, 2021, p.64-67
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    Modeling the Operation of Charge Trap Flash Memory–Part I: The Importance of Carrier Energy Relaxation

    Schanovsky, F.
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    Verreck, Devin  
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    Stanojevic, Z.
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    Schallert, S.
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    Arreghini, Antonio  
    Journal article
    2024, IEEE TRANSACTIONS ON ELECTRON DEVICES, (71) 1, p.547-553
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    Monolithic TCAD simulation of phase-change memory (PCM/PRAM) plus Ovonic Threshold Switch (OTS) selector device

    Thesberg, M.
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    Stanojevic, Z.
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    Baumgartner, O.
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    Kernstock, C.
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    Leonelli, D.
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    Barci, M.
    ;
    Wang, X.
    Journal article
    2023, SOLID-STATE ELECTRONICS, (199) January, p.Art.: 108504
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    Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies

    Rzepa, G.
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    Karner, M.
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    Baumgartner, O.
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    Strof, G.
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    Schanovsky, F.
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    Mitterbauer, F.
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    Kernstock, C.
    Proceedings paper
    2021, IEEE International Reliability Physics Symposium (IRPS), MAR 21-24, 2021
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    Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling

    Verreck, Devin  
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    Arreghini, Antonio  
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    Schanovsky, F.
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    Rzepa, G.
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    Stanojevic, Z.
    ;
    Mitterbauer, F.
    Proceedings paper
    2021, IEEE International Electron Devices Meeting (IEDM), DEC 11-16, 2021

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