Browsing by Author "Vassilev, Vesselin"
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Publication A 1.3dB NF CMOS LNA for GPS with 3kV HBM ESD-protection
Proceedings paper2002-09, Proceedings European Solid-State Circuit Conference - ESSCIRC, 23/09/2002, p.335-338Publication A 1.6dB NF CMOS LNA for GPS with 3kV HBM ESD-protection
Proceedings paper2002, Proceedings 24th EOS/ESD Symposium, 6/10/2002, p.18-25Publication A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits
;Vassilev, Vesselin ;Vaschenko, Vladislav ;Jansen, Philippe ;Choi, B.-J.Concannon, AnJournal article2004, Microelectronics Reliability, (44) 9_11, p.1885-1890Publication A compact MOSFET breakdown model for optimization of gate coupled ESD protection circuits
Proceedings paper1999, ESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference; 13-15 September 1999; Leuven, Belgium., p.600-603Publication Advanced modeling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies
Proceedings paper2004, Electrical Overstress / Electrostatic Discharge Symposium Proceedings, 19/09/2004, p.2.B.1Publication Analysis and improved compact modelling of the breakdown behaviour of sub-0.25 micron ESD protection ggNMOS devices
Proceedings paper2001, Electrical Overstress/Electrostratic Discharge Syymposium Proceedings - EOS/ESD, 11/09/2001, p.461-468Publication CAD assisted ESD protection optimization for advanced digital and RF CMOS applications
Vassilev, VesselinPHD thesis2004-09Publication Co-design methodology to provide high esd protection levels in the advanced rf circuits
;Vassilev, Vesselin; ;Lajo-Segura, P.; ; Leroux, P.Proceedings paper2003-09, Proceedings EOS/ESD Symposium, 21/09/2003, p.195-203Publication Design-driven optimisation of a 90 nm RF CMOS process by use of elevated source/drain
Proceedings paper2003-09, 33rd European Solid-State Devices Research Conference - ESSDERC, 16/09/2003, p.43-46Publication Dynamic substrate resistance snapback of ESD protection devices
Proceedings paper2003, Proceedings 41st Annual IEEE International Reliability Physics Symposium, 30/03/2003, p.256-260Publication Enhanced ESD protection robustness of a lateral NPN structure in the advanced CMOS
Proceedings paper2004, Proceedings IEEE International Reliability Physics Symposium - IRPS, 25/04/2004, p.605-606Publication ESD circuit model based protection network optimisation for extended-voltage NMOS drivers
Journal article2005-10, Micrelectronics Reliability, (45) 9_11, p.1430-1435Publication ESD protection challenges in RFCMOS circuits - an overview
Oral presentation2004, IEEE International Symposium on Microwaves - ISMPublication ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS implementation concepts, constraints and solutions
Proceedings paper2005-11, RCJ Symposium, 10/11/2005, p.97-106Publication ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS implementation concepts, constraints and solutions
Proceedings paper2004, Electrical Overstress / Electrostatic Discharge Symposium Proceedings, 19/09/2004, p.1.B.2Publication ESD reliability issues in RF CMOS circuits
Proceedings paper2002, Proceedings of the International Workshop on Semiconductor devices, 11/12/2001, p.551-556Publication ESD reliability issues in sub-micron CMOS - trends and challenges
Oral presentation2003, 2nd MRS Int. Conf. on Materials for Advanced Technologies & IUMRSPublication ESD-RF co-design methodology for the state of the art RF-CMOS blocks
Journal article2005, Microelectronics and Reliability, (45) 2, p.255-268Publication High ESD performance, low power CMOS LNS for GPS applications
;Leroux, P. ;Vassilev, Vesselin ;Steyaert, M.Maes, HermanJournal article2003, Journal of Electrostatics, (59) 3_4, p.179-192Publication High frequency characterization and modelling of the parasitic RC performance of two terminal ESD CMOS protection devices
Journal article2003, Microelectronics Reliability, (43) 7, p.1011-1020