Browsing by Author "Xiang, Yang"

A BSIM-Based Predictive Hot-Carrier Aging Compact Model

A Direct-Capacitance-Conversion FeRAM Characterization Platform for Enabling Non-Destructive 3-D Ferroelectric Capacitor Readout

A DTCO Framework for 3D NAND Flash Readout

Built-in sheet charge as an alternative to dopant pockets in tunnel field-effect transistors

CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark

Compact Modeling and Design Exploration of Non-Destructive Read-Out 1T1C FeRAM

Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics

Design enablement of CFET devices for sub-2nm CMOS nodes

Design Space Exploration of FeRAM Bit Cell for DRAM Application

Enhanced Capacitive Memory Window by Improving Remnant Polarization in Ferroelectric Capacitors for Non-Destructive Read

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3 nm Era

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect

Gate oxide reliability: upcoming trends, challenges, and opportunities

High-Density Standard Cell Libraries with Backside Power Options in A14 Nanosheet Node

Implication of Channel Percolation in Ferroelectric FETs for Threshold Voltage Shift Modeling

Improved Capacitive Memory Window for Non-destructive Read in HZO-based Ferroelectric Capacitors with Incorporation of Semiconducting IGZO

Physical insights on steep slope FEFETs including nucleation-propagation and charge trapping

PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch

Process-induced power-performance variability in sub-5nm III-V tunnel FETs