Browsing by author "Yoshida, Naomi"

Now showing items 1-6 of 6

3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors

Eyben, Pierre; Ritzenthaler, Romain; De Keersgieter, An; Chiarella, Thomas; Veloso, Anabela; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Machillot, Jerome; Kim, Myungsun; Miyashita, Toshihiko; Yoshida, Naomi; Bender, Hugo; Richard, Olivier; Celano, Umberto; Paredis, Kristof; Wouters, Lennaert; Mitard, Jerome; Horiguchi, Naoto (2019)
Highly scalable bulk FinFET devices with multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond

Ragnarsson, Lars-Ake; Chew, Soon Aik; Dekkers, Harold; Toledano Luque, Maria; Parvais, Bertrand; De Keersgieter, An; Van Ammel, Annemie; Schram, Tom; Yoshida, Naomi; Phatak, Anup; Han, Keping; Colombeau, Benjamin; Brand, Adam; Horiguchi, Naoto; Thean, Aaron (2014)
RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs

Ragnarsson, Lars-Ake; Dekkers, Harold; Schram, Tom; Chew, Soon Aik; Parvais, Bertrand; Dehan, Morin; Devriendt, Katia; Tao, Zheng; Sebaai, Farid; Baerts, Christina; Van Elshocht, Sven; Yoshida, Naomi; Phatak, Anup; Lazik, Christoph; Brand, Adam; Clark, William; Fried, David; Mocuta, Dan; Barla, Kathy; Horiguchi, Naoto; Thean, Aaron (2015)
Scaled, novel effective workfunction metal gate stacks for advanced Low-VT, gate-all-around vertically stacked nanosheet FETs with reduced vertical distance between sheets

Veloso, Anabela; Simoen, Eddy; Oliveira, Alberto; Vaisman Chasin, Adrian; Chen, S.-C.; Lin, Y.; Miyashita, T.; Kim, M.; Jang, Doyoung; Ritzenthaler, Romain; Zhou, Daisy; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Kenis, Karine; Sebaai, Farid; Mannaert, Geert; Devriendt, Katia; Hopf, Toby; Versluijs, Janko; Richard, Olivier; Machillot, Jerome; Yoshida, Naomi; Horiguchi, Naoto (2019)
Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization

Ritzenthaler, Romain; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Vaisman Chasin, Adrian; Kenis, Karine; Devriendt, Katia; Mannaert, Geert; Dekkers, Harold; Dangol, Anish; Lin, Yongjin; Sun, Shiyu; Chen, Zhebo; Kim, Myungsun; Chen, ShiChung; Machillot, Jerome; Mitard, Jerome; Yoshida, Naomi; Kim, Namsung; Mocuta, Dan; Horiguchi, Naoto (2018)
Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration

Mertens, Hans; Ritzenthaler, Romain; Pena, Vanessa; Santoro, Gaetano; Kenis, Karine; Schulze, Andreas; Dentoni Litta, Eugenio; Chew, Soon Aik; Devriendt, Katia; Chiarella, Thomas; Demuynck, Steven; Yakimets, Dmitry; Jang, Doyoung; Spessot, Alessio; Eneman, Geert; Dangol, Anish; Lagrain, Pieter; Bender, Hugo; Sun, Shiyu; Korolik, Michael; Kioussis, D.; Kim, Myungsun; Bu, Kyung-Ho; Chen, Shih Chung; Cogorno, Matt; Devrajan, J.; Machillot, Jerome; Yoshida, Naomi; Kim, Namsung; Barla, Kathy; Mocuta, Dan; Horiguchi, Naoto (2017)

Browsing by author "Yoshida, Naomi"

3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors ﻿

Highly scalable bulk FinFET devices with multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond ﻿

RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs ﻿

Scaled, novel effective workfunction metal gate stacks for advanced Low-VT, gate-all-around vertically stacked nanosheet FETs with reduced vertical distance between sheets ﻿

Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization ﻿

Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration ﻿

3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors

Highly scalable bulk FinFET devices with multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond

RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs

Scaled, novel effective workfunction metal gate stacks for advanced Low-VT, gate-all-around vertically stacked nanosheet FETs with reduced vertical distance between sheets

Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization

Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration