Browsing by author "Salahuddin, Shairfe Muhammad"
Now showing items 1-16 of 16
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3D SRAM Macro Design in 3D Nanofabric Process Technology
Abdi, Dawit; Salahuddin, Shairfe Muhammad; Boemmels, Juergen; Giacomin, Edouard; Weckx, Pieter; Ryckaert, Julien; Hellings, Geert; Catthoor, Francky (2023) -
3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes
Chen, Rongmei; Weckx, Pieter; Salahuddin, Shairfe Muhammad; Kim, Soon-Wook; Sisto, Giuliano; Van der Plas, Geert; Stucchi, Michele; Baert, Rogier; Debacker, Peter; Na, Myung Hee; Ryckaert, Julien; Milojevic, Dragomir; Beyne, Eric (2020) -
Buried Bitline for sub-5nm SRAM Design
Mathur, R.; Bhargava, M.; Annamalai, S.; Chong, Y. K.; Sinha, S.; Cline, B.; Kulkarni, J. P.; Salahuddin, Shairfe Muhammad; Schuddinck, Pieter; Ryckaert, Julien; Gupta, Anshul (2020) -
Buried Interconnects for Sub-5 nm SRAM Design
Mathur, R.; Bhargava, M.; Cline, B.; Salahuddin, Shairfe Muhammad; Gupta, Anshul; Schuddinck, Pieter; Ryckaert, Julien; Kulkarni, J.P. (2022) -
Buried Power Rail Metal exploration towards the 1 nm Node
Gupta, Anshul; Radisic, Dunja; Maes, J.W.; Varela Pedreira, Olalla; Soulie, Jean-Philippe; Jourdan, Nicolas; Mertens, Hans; Bandyopadhyay, Sudip; Le, Quoc Toan; Pacco, Antoine; Heylen, Nancy; Vandersmissen, Kevin; Devriendt, Katia; Zhu, C.; Datta, S.; Sebaai, Farid; Wang, S.; Mousa, M.; Lee, J.; Geypen, Jef; De Wachter, Bart; Chehab, Bilal; Salahuddin, Shairfe Muhammad; Murdoch, Gayle; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021) -
Buried power SRAM DTCO and system-level benchmarking in N3
Salahuddin, Shairfe Muhammad; Perumkunnil, Manu; Dentoni Litta, Eugenio; Gupta, Anshul; Weckx, Pieter; Ryckaert, Julien; Na, Myung Hee; Spessot, Alessio (2020) -
CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling
Liu, Hsiao-Hsuan; Salahuddin, Shairfe Muhammad; Chan, Boon Teik; Schuddinck, Pieter; Xiang, Yang; Hellings, Geert; Weckx, Pieter; Ryckaert, Julien; Catthoor, Francky (2023) -
CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark
Liu, Hsiao-Hsuan; Schuddinck, Pieter; Pei, Zhenlin; Verschueren, Lynn; Mertens, Hans; Salahuddin, Shairfe Muhammad; Hiblot, Gaspard; Xiang, Yang; Chan, Boon Teik; Subramanian, Sujith; Weckx, Pieter; Hellings, Geert; Garcia Bardon, Marie; Ryckaert, Julien; Pan, Chenyun; Catthoor, Francky (2023) -
Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node
Chen, Rongmei; Sisto, Giuliano; Jourdain, Anne; Hiblot, Gaspard; Stucchi, Michele; Kakarla, Naveen; Chehab, Bilal; Salahuddin, Shairfe Muhammad; Schleicher, Filip; Veloso, Anabela; Hellings, Geert; Weckx, Pieter; Milojevic, Dragomir; Van der Plas, Geert; Ryckaert, Julien; Beyne, Eric (2021) -
Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access
Pei, Zhenlin; Mayahinia, Mahta; Liu, Hsiao-Hsuan; Tahoori, Mehdi; Salahuddin, Shairfe Muhammad; Catthoor, Francky; Tokei, Zsolt; Pan, Chenyun (2023) -
Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node
Liu, Hsiao-Hsuan; Salahuddin, Shairfe Muhammad; Abdi, Dawit; Chen, Rongmei; Weckx, Pieter; Matagne, Philippe; Catthoor, Francky (2022) -
From Design to System-Technology optimization for CMOS
Ryckaert, Julien; Chehab, Bilal; Jang, Doyoung; Mirabelli, Gioele; Salahuddin, Shairfe Muhammad; Schuddinck, Pieter; Zografos, Odysseas; Ahmed, Zubair; Weckx, Pieter; Hellings, Geert (2021) -
SRAM with buried power distribution to improve write margin and performance in advanced technology nodes
Salahuddin, Shairfe Muhammad; Shaik, Khaja Ahmad; Gupta, Anshul; Chava, Bharani; Gupta, Mohit; Weckx, Pieter; Ryckaert, Julien; Spessot, Alessio (2019) -
System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs
Perumkunnil, Manu; Yasin, Farrukh; Rao, Siddharth; Salahuddin, Shairfe Muhammad; Milojevic, Dragomir; Van der Plas, Geert; Ryckaert, Julien; Beyne, Eric; Furnemont, Arnaud; Kar, Gouri Sankar (2020) -
Thermal stress-aware CMOS-SRAM partitioning in sequential 3-D technology
Salahuddin, Shairfe Muhammad; Dentoni Litta, Eugenio; Gupta, Anshul; Ritzenthaler, Romain; Schaekers, Marc; Everaert, Jean-Luc; Yu, Hao; Vandooren, Anne; Ryckaert, Julien; Na, Myung Hee; Spessot, Alessio (2020) -
Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations
Spessot, Alessio; Salahuddin, Shairfe Muhammad; Escobar Gavilanez, Ricardo; Ritzenthaler, Romain; Xiang, Yang; Budhwani, Rahul Kumar; Dentoni Litta, Eugenio; Capogreco, Elena; Bastos, Joao; Chen, Yangyin; Horiguchi, Naoto (2022)